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Data Sheet
SAA7378GP Single Chip Digital Servo Processor and Compact Disc Decoder (CD7)
Preliminary specification: Version 1.0
May1995
Philips Semiconductors
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
1. * * * * * * * * * * * *
FEATURES Single speed mode. Full error correction strategy, t = 2 and e = 4. All standard decoder functions implemented digitally on chip. FIFO overflow concealment for rotational shock resistance. Digital audio interface (EBU), audio only. 2 - 4 times oversampling integrated digital filter. Audio data peak level detection. Kill interface for DAC deactivation during digital silence. All TDA1301 (DSIC2) digital servo functions, plus extra hi-level functions. Low focus noise. Communication via TDA1301/SAA7345 compatible bus. On chip clock multiplier allows the use of 8.4672MHz crystal.
GENERAL DESCRIPTION 2. CD7 (SAA7378GP) is a single chip combining the functions of a CD decoder IC and Digital Servo IC. The decoder part is based on CD6 (SAA7345GP) with an improved error correction strategy; the servo part is based on DSIC2 (TDA1301T) with improvements incorporated. 3. QUICK REFERENCE DATA SYMBOL VDD IDD fXTAL Tamb Tstg 4. supply current crystal frequency operating ambient temperature storage temperature ORDERING INFORMATION EXTENDED TYPE NUMBER SAA7378GP PACKAGE PINS 64 PIN POSITION QFP MATERIAL plastic CODE SOT393-1 PARAMETER supply voltage MIN 3.4 8 5 -55 TYP 5.0 49 8.4672 MAX 5.5 35 +70 +125 UNIT V mA MHz C C
Note 1. When using reflow soldering it is recommended that the Dry Packing instructions in the " Quality Reference Pocketbook" are followed. The pocketbook can be ordered using the code 9398 510 34011. Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
May 1995
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
R1 OUTPUT STAGES R2 ADC PREPROCESSING CONTROL FUNCTION RA FO SL
VRH SCL SDA RAB SILD
VREF GENERATOR MICRO PROCESSOR INTEFACE CONTROL PART
VDD3C
VDD1P
VDD2P
VDDA1
VDDA2
VSSA2
VSSA1
VSSA3
IREFT
VSS1
VSS2
VSS3
VSS4
VRL
D1
D2
D3
D4
LDON
HFIN FRONT END HFREF ISLICE IREF EFM DEMODULATOR TEST1 TEST2 TEST3 SELPLL CRIN TIMING CROUT CL16 CL11 CL4 TEST4 TEST5 TEST7 TEST6 TEST9 DECODER MICROPROCESSOR INTERFACE RESET SUBCODE PROCESSOR SERIAL DATA INTERFACE PEAK DETECT SCLK WCLK DATA SRAM AUDIO PROCESSOR TEST10 TEST FLAGS ERROR CORRECTOR CFLG DIGITAL PLL MOTO1 MOTOR CONTROL MOTO2
INTERFACE
RAM ADDRESSER EBU
DOBM
VERSATILE PINS INTERFACE
KILL TEST8
V1
V2
V3
V4
V5
Figure 1
Functional Block Diagram
May 1995
3
KILL
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
5. PIN DESCRIPTION SYMBOL VSSA1 VDDA1 D1 D2 D3 VRL D4 R1 R2 IREFT VRH VSSA2 SELPLL ISLICE HFIN VSSA3 HFREF IREF VDDA2 TEST1 CRIN CROUT TEST2 CL16 CL11 RA FO SL TEST3 VDD1P DOBM VSS1 MOTO1 MOTO2 TEST4 TEST5 May 1995 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 analogue supply* analogue supply* unipolar current input (central diode signal input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) reference input for ADC unipolar current input (central diode signal input) unipolar current input (satellite diode signal input) unipolar current input (satellite diode signal input) current reference for calibration ADC reference output from ADC analogue supply* selects whether internal clock multiplier PLL is used current feedback from data slicer comparator signal input analogue supply* comparator common mode input reference current pin (nominally VDD/2) analogue supply* test control input; this pin should be tied LOW crystal/resonator input crystal/resonator output test control input; this pin should be tied LOW 16.9344 MHz system clock output 11.2896 MHz or 5.6448MHz clock output (tri-state) radial actuator output focus actuator output sledge control output test control input; this pin should be tied LOW digital supply periphery* bi-phase mark output (externally buffered) (tri-state) digital supply* motor output 1; versatile (tri-state) motor output 2; versatile (tri-state) test output pin; this pin should be left unconnected test output pin; this pin should be left unconnected 4 DESCRIPTION
SAA7378GP
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
SYMBOL TEST6 TEST7 VSS2 V5 V4 V3 KILL TEST8 DATA WCLK VDD2P SCLK VSS3 CL4 SDA SCL RAB SILD N/C VSS4 RESET TEST9 VDD3C TEST10 CFLG V1 V2 LDON
PIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
DESCRIPTION test input; this pin should be tied LOW test output pin; this pin should be left unconnected digital supply* versatile output pin versatile output pin versatile output pin (open drain) kill output - programmable (open drain) test output pin; this pin should be left unconnected serial data output (tri-state) word clock output (tri-state) digital supply periphery* serial bit clock output (tri-state) digital supply* 4.2336 MHz P clock output P interface data I/O line (open drain output) P interface clock line P interface R/W and load control line P interface R/W and load control line No connection digital supply* power-on reset input (active low) test output pin; this pin should be left unconnected digital supply core* test output pin; this pin should be left unconnected correction flag output (open drain) versatile input pin versatile input pin laser drive on output (open drain)
* Note: All supply pins must be connected to the same external power supply voltage.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
TEST10
RESET
TEST9
VDD3C
LDON
CFLG
VSS4
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
VSSA1 VDDA1 D1 D2 D3 VRL D4 R1 R2 IREFT VRH VSSA2
1 2 3 4 5 6 7 8 9 10 11 12
49 48 47 46 45 44 43 42
VSS3
SILD
RAB
SDA
SCL
CL4
NC
V2
V1
SCLK VDD2P WCLK DATA TEST8 KILL V3 V4 V5 VSS2 TEST7 TEST6 TEST5 TEST4 MOTO2 MOTO1
SAA7378
41 40 39 38 37 36 35 34 33
SELPLL 13 ISLICE HFIN VSSA3 14 15 16
17
18
20
21
22
23
24
29
30
31 DOBM
19
25
26
27
CROUT
HFREF
TEST1
TEST2
28
TEST3
VDDA2
VDD1P
CL16
CRIN
CL11
IREF
RA
FO
Figure 2
Pinning Diagram
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6
SL
VSS1
32
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
6.
SYMBOL VDD VI(max) VO VDDDIFF IO IIK Tamb Tstg Ves1 Ves2 Notes: 1) 2) 3) supply voltage maximum Input voltage (any input) Output voltage (any output) Difference between VDDA and VDDD Output current (continuous) DC input diode current (continuous) operating ambient temperature storage temperature electrostatic handling electrostatic handling note 2 note 3 5 -55 -2000 -200
SAA7378GP
LIMITING VALUES
PARAMETER CONDITIONS note 1 MIN -0.5 -0.5 -0.5 MAX +6.5 VDD + 0.5 +6.5 0.25 20 20 +70 +125 +2000 +200 UNIT V V V V mA mA C C V V
In accordance with the Absolute Maximum Rating System (IEC 134).
All VDD and VSS connections must be made externally to the same power supply. Equivalent to discharging a 100pF capacitor via a 1.5k series resistor with a rise time of 15ns. Equivalent to discharging a 200pF capacitor via a 2.5H series inductor.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7. 7.1 FUNCTIONAL DESCRIPTION OF THE DECODER PART Principle Operation Modes of the Decoder Part
SAA7378GP
The decoding part operates at single speed and supports a full audio specification. A simplified data flow through the decoder part is shown in Figure 5.
7.1.1
Crystal Frequency Selection
The SAA7378 which has an internal phase locked loop clock multiplier, can be used with 33.8688, 16.9344 or 8.4672MHz crystal frequencies by setting register B and SELPLL as shown below. Register B 00xx 00xx 01xx SELPLL 0 1 0 crystal frequency (MHz) 33.8688 8.4672 16.9344
The internal clock multiplier, controlled by SELPLL, should only be used if an 8.4672MHz crystal, ceramic resonator or external clock is present. Note: The CL11 output is a 5.6448MHz clock if a 16.9344MHz external clock is used.
7.1.2
Standby Modes
"CD-STOP" mode. Most I/O functions are switched off. "CD-PAUSE" mode. Audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. This is also called a "Hot Pause".
The SAA7378 may be placed in two standby modes, (Note that the device core is still active), selected by register B : Standby 1 : Standby 2:
In the standby modes the various pins will have following values: MOTO1, MOTO2: SCL,SDA, SILD, RAB: SCLK, WCLK, DATA, CL11, DOBM: CRIN, CROUT, CL16, CL4: V1, V2, V3, V4, V5, CFLG: Put in Hi-z, PWM mode (standby 1 and reset : operating in standby 2). Put in Hi-z, PDM mode (standby1 and reset: operating in standby 2). No interaction. Normal operation continues. Tri-state in both standby modes. Normal operation continues after reset. No interaction. Normal operation continues. No interaction. Normal operation continues.
7.2
Crystal Oscillator
The crystal oscillator is a conventional 2 pin design operating at 8 MHz to 35 MHz. This oscillator is capable of working with ceramic resonators as well as with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown below in Figure 3. Typical oscillation frequencies required are 8.4672MHz, 16.9344MHz or 33.8688MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
SAA7378
Oscillator
CROUT
330 100k 22pF 22pF 8.4672MHz
CRIN
8.4672MHz Fundamental Configuration
SAA7378
Oscillator
CROUT
330 3.3H 100k 10pF 10pF 1nF 33.8688MHz
CRIN
33.8688MHz 3rd Overtone Configuration
Figure 3
Crystal Oscillator Circuits
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7.3 Data Slicer and Clock Regenerator
SAA7378GP
The SAA7378 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if SELPLL is set high while using an 8.4672MHz crystal, and register 4 is set to 0xxx). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL).
crystal clock 2.2nF HF input 47pF 2.2k
HFIN DQ
+ HFREF
22k VDD/2 DPLL
IREF
22nF
100 A
VSSA
100nF
VSS ISLICE VDD
100 A
VSSA
Figure 4
Data Slicer Showing Typical Application Components
Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. For certain applications an offtrack input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is high, the SAA7378 will assume that its servo part is following on the wrong track, and will flag all incoming HF data as incorrect.
7.4 7.4.1
Demodulator Frame Sync Protection
A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. The master counter is only reset if: - a sync coincidence detected; sync pattern occurs 588 1 EFM clocks after the previous sync pattern. - a new sync pattern is detected within 6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the PLL lock signal, which is active high after 1 sync coincidence found, and reset low if during 61 consecutive frames no sync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by register 2 and 7. Also incorporated in the demodulator is a RL2 (Run Length 2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability.
7.4.2 EFM Demodulation The 14-bit EFM data and subcode words are decoded into 8-bit symbols.
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Philips Semiconductors
P INTERFACE SDA EBU INTERFACE DOBM reg A 1 : no preemphasis detected OR reg D = 01xx (deemphasis signal at V5) 0 : preemphasis detected AND reg D 01xx PHASE COMPENSATION 1 0 DIGITAL FILTER IIS INTERFACE SCLK WCLK DATA reg 3 reg 3 DEEMPHASIS FILTER
SUBCODE PROCESSOR
output from data slicer
DIGITAL PLL & DEMODULATOR
Digital Servo Processor and Compact Disc Decoder (CD7)
11
KILL KILL V3 reg C
FIFO
ERROR CORRECTOR
FADE/MUTE/ INTERPOLATE
Preliminary specification: Version 1.0
SAA7378GP
Figure 5
SAA7378 Decoder Function: Simplified Data Flow
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7.5 7.5.1 Subcode Data Processing Q-Channel Processing
SAA7378GP
The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go low. SUBQREADY-I can be read via the SDA or STATUS pins, selected via register 2. Good Q-channel data may be read from SDA.
7.5.2
Subcode Channels Q-W
Data of subcode channels, Q-W, is available in the EBU output (DOBM).
7.6
FIFO and Error Corrector
The SAA7378 has a 8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM).
7.6.1
Flags Output (CFLG)
The flags output pin CFLG (open-drain) shows the status of the error corrector and interpolator and is updated every frame 7.35kHz. In the SAA7378 chip a 1-bit flag is present on the CFLG pin as shown in Figure 6.This signal shows the status of the error corrector and interpolator.
33.9 s
11.3 s
33.9s
F8
F1
F2
F3
F4
F5
F6
F7
F8
F1
Figure 6
Flag Output Timing Diagram
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
F1 0 1 x x x x x x x x x x x x x x
F2 x x 0 0 1 1 x x x x x x x x x x
F3 x x 0 1 0 1 x x x x x x x x x x
F4 x x x x x x 0 0 0 0 1 1 x x x x
F5 x x x x x x 0 0 1 1 0 1 x x x x
F6 x x x x x x x x x x x x 0 0 1 1
F7 x x x x x x x x x x x x 0 1 0 1
F8 x x x x x x 0 1 0 1 0 1 x x x x No Absolute Time sync Absolute Time sync C1 frame contained no errors C1 frame contained 1 error C1 frame contained 2 errors C1 frame uncorrectable C2 frame contained no errors C2 frame contained 1 error C2 frame contained 2 errors C2 frame contained 3 error C2 frame contained 4 errors C2 frame uncorrectable No interpolations
MEANING
At least one 1-sample interpolation At least one hold and no interpolations At least one hold and one 1-sample interpolation
The first flag bit, F1, is the absolute time sync signal; the FIFO-passed subcode-sync and relates the position of the subcodesync to the audio data (DAC output). The output flags can be made available at bit 4 of the EBU data format (LSB of the 24bit data word), if selected by register A.
7.7 7.7.1
Audio Functions Deemphasis and Phase Linearity
When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a deemphasis filter section. When deemphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 - 16 kHz. With deemphasis the filter is not phase linear. If the deemphasis signal is set to be available at V5, selected via register D, then the deemphasis filter is bypassed.
7.7.2
Digital Oversampling Filter
The SAA7378 contains a 2 - 4 times oversampling IIR filter. The filter specification of the 4 x oversampling filter is given in the table below.
PASSBAND 0 - 19 kHz 19 - 20 kHz STOPBAND 24.0 kHz 24 - 27 kHz 27 - 35 kHz 35 - 64 kHz 64 - 68 kHz 68 kHz 69 - 88 kHz ATTENUATION 0.001 dB 0.03 dB ATTENUATION 25 dB 38 dB 40 dB 50 dB 31 dB 35 dB 40 dB
These attenuations do not include the sample and hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled -0.5 dB down, to avoid overflow on full scale sine wave inputs (0 - 20 kHz).
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7.7.3 Concealment
SAA7378GP
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1sample linear interpolation is then performed before the next good sample (Figure 7). .
Interpolation
Hold
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
Figure 7
Concealment Mechanism
7.7.4
Mute, Full Scale, Attenuation and Fade
A digital level controller is present on the SAA7378 which performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0. Mute: Attenuate: Full scale: Fade: signal reduced to 0 in a maximum of 128 steps; 3ms. signal scaled by -12dB. ramp signal back to 0dB level. From mute takes 3ms. activates a 128 stage counter which allows the signal to be scaled up/down by 0.07dB steps. 128 = full scale 120 = -0.5dB (ie. full scale if oversampling filter used) 32 = -12dB 0 = mute
7.7.5
Peak Detector
The peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via SDA.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7.8 DAC Interface
SAA7378GP
The SAA7378 is compatible with a wide range of Digital-Analogue Converters. Six formats are supported and are shown below. Figure 8 and Figure 9 show the Philips IIS and the EIAJ data formats respectively. All formats are MSB first and fs is 44.1kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7.
REGISTER 3 0000 0100 1100 0011 0111 1111 SAMPLE FREQUENCY 4fs 4fs 4fs 2fs 2fs 2fs No of BITS 16 18 18 16 18 18 SCLK MHz 8.4672 * n 8.4672 * n 8.4672 * n 4.2336 * n 4.2336 * n 4.2336 * n FORMAT EIAJ - 16 bits EIAJ - 18 bits Philips I2S - 18 bits EIAJ - 16 bits EIAJ - 18 bits Philips I2S - 18 bits INTERPOLATION yes yes yes yes yes yes
SCLK DATA WCLK Figure 8 Philips I2S Data Format (18-Bit Word Length Shown)
10 17 16 10 1514
LEFT CHANNEL DATA (WCLK NORMAL POLARITY)
SCLK DATA WCLK 0
17 LEFT CHANNEL DATA 0 17
Figure 9
EIAJ Data Format (18-Bit Word Length Shown)
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7.9 EBU Interface
SAA7378GP
The biphasemark digital output signal at pin DOBM is according to the format defined by the IEC958 specification. The DOBM pin can be held low; selected via register A:
7.9.1
Format
The digital audio output consists of 32-bit words ("subframes") transmitted in biphasemark code (two transitions for a logic'1' and one transition for a logic'0'). Words are transmitted in blocks of 384.
sync auxiliary error flags audio sample validity flag user data channel status parity bit bits 0 - 3 bits 4 - 7 bit 4 bits 8 - 27 bit 28 bit 29 bit 30 bit 31 Not used. Normally zero CFLG error and interpolation flags when selected by register A First 4 bits not used (always zero). 2's compliment. LSB = bit 12, MSB = bit 27 Valid = logic 0 Used for subcode data (Q to W) Control bits and category code Even parity for bits 4 to 30
Sync:
The Sync word is formed by violation of the biphase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: Sync B:- Start of a block (384 words), word contains left sample. Sync M:- Word contains left sample (no block start). Sync W:- Word contains right sample. Audio sample: Left and right samples are transmitted alternately. Validity flag: Audio samples are flagged (bit 28 = '1') if an error has been detected but was uncorrectable. This flag remains the same even if data is taken after concealment User data: Subcode bits Q until W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. Channel status: The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is shown below.
control bits 0 - 3 copy of CRC checked Q-channel control bits 0 - 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has preemphasis always zero. CD: bit 8 = logic1, all other bits = logic 0 set by register A: 10 = level I 00 = level II 01 = level III always zero
reserved mode category code clock accuracy
bits 4 - 7 bits 8 - 15 bits 28 - 29
remaining
bits 16 - 27 bits 30 - 191
7.10
KILL Circuit
The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before the digital filter. The output is switched active-low when silence has been detected for at least 250ms, or if Mute is active. Two modes are available, selected by register C: - 1 pin kill: KILL active low indicates silence detected on both left and right channels. - 2 pin kill: KILL active low indicates silence detected on left channel. V3 active low indicates silence detected on right channel.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
7.11 The VIA Interface
PIN NAME PIN no. TYPE CONTROL REGISTER ADDRESS 1100 CONTROL REGISTER DATA xxx1 xxx0 FUNCTION
SAA7378GP
The SAA7378 has five pins that can be reconfigured for different applications:
V1
62
Input
External offtrack signal input Internal offtrack signal used Input may be read via decoder status bit; selected via register 2. Input may be read via decoder status bit; selected via register 2.
V2 V3
63 42
Input Output 1100 xx0x x01x x11x
Kill output for Right channel Output = 0 Output = 1 4-line motor drive (using V4 & V5) Output = 0 Output = 1 Deemphasis output (active high) Output = 0 Output = 1
V4
41
Output
1101
0000 xx10 xx11
V5
40
Output
1101
01xx 10xx 11xx
7.12 7.12.1
Spindle Motor Control Motor Output Modes
The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and Disc speed information are used to calculate the motor control output signals. Several output modes, selected by register 6, are supported: - Pulse Density, 2-line (true complement output), 1MHz sample frequency. - PWM-output, 2-line, 22.05kHz modulation frequency. - PWM-output, 4-line, 22.05kHz modulation frequency. - CDV motor mode.
7.12.1.1
Pulse Density Output Mode
In the Pulse Density mode the motor output pin, MOTO1, is the pulse density modulated motor output signal. 50% duty cycle corresponds with the motor not actuated, higher duty cycles mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a 1MHz internal clock signal. Possible application diagrams are shown in Figure 10.
7.12.1.2
PWM Output Mode, 2-Line
In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output, and the motor braking signal is pulse-width modulated on the MOTO2 output. Figure 11 shows the timing and Figure 12 a typical application diagram.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
22 k
22 k
MOTO1
10n VSS VDD 22 k 22 k
+ -
M
+ -
MOTO2
10n VSS
MOTO1
22 k VSS 10 n VSS
+ 22 k 22 k VDD
M
VSS
Figure 10
Motor Pulse Density Application Diagrams
trep = 45 s MOTO1 MOTO2 Accelerate
tdead = > 240 ns
Brake
Figure 11
2-Line PWM Mode Timing
+
10 M
100n
MOTO1
MOTO2
VSS
Figure 12
Motor 2-Line PWM Mode Application Diagram
7.12.1.3
PWM Output Mode, 4-Line
Using two extra outputs from the Versatile Pins Interface, it is possible to use the SAA7378 with a 4-input motor bridge.
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Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
Figure 13 shows the timing, and Figure 14 a typical application diagram.
SAA7378GP
trep = 45 s
tdead = > 240 ns
MOTO1 MOTO2 V4 V5
Accelerate tovl = 240 ns Brake
Figure 13
4-Line PWM Mode Timing
+ V4 V5
10 M
100n
MOTO1
VSS
MOTO2
Figure 14
Motor 4-Line PWM Mode Application Diagram
7.12.1.4
CDV/CAV Output Mode
In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin (carrier frequency 300Hz), and the PLL frequency signal will be put in pulse-density modulated form (carrier frequency 4.23MHz) on the MOTO2 pin. The integrated motor servo is disabled in this mode. Notes: 1) The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half full) will result in a PWM output of 60%.
7.12.2
Spindle Motor Operating Modes
The motor servo has the following operation modes controlled by register 1: Start mode 1 Disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved and the PLL is reset. No Disc speed information is available for the P. Start mode 2 The Disc is accelerated as in Start mode 1, however the PLL will monitor the Disc speed. When the Disc reaches 75% of its nominal speed, the controller will switch to Jump mode. The motor status signals selectable via register 2 are valid. Jump mode Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is possible to read the subcode. Jump mode 1 Similar to Jump mode but motor integrator is kept at zero. Used for long jumps, where there is a large change in disc speed.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
Play mode FIFO released after resetting to 50%. Audio mute released. Stop mode 1 Disc is braked by applying a negative voltage to the motor. No decisions are involved. Stop mode 2 The Disc is braked as in Stop mode 1, but the PLL will monitor the Disc speed. As soon as the Disc reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal speed, the MOTSTOP status signal will go high and switch the motor servo to Off mode. Off mode Motor not steered. In the SAA7378 decoder there is an anti-wind-up mode for the motor servo, selected via register 1. When the anti-wind-up mode is activated the motor servo integrator will hold if the motor output saturates.
7.12.2.1
Power Limit
In Start mode 1, Start mode 2, Stop mode 1 and Stop mode 2, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. The following power limits are possible: 100% (no power limit), 75%, 50%, or 37% of maximum.
7.12.3
Loop Characteristics
The gain and crossover frequencies of the motor control loop can be programmed via registers 4 and 5. The following parameter values are possible: Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6, 32 Crossover frequency f4: 0.5Hz, 0.7Hz, 1.4Hz, 2.8Hz Crossover frequency f3: 0.85Hz, 1.71Hz, 3.42Hz
A
f4
f3
BW
f
Figure 15
Motor Servo Bode Diagram
7.12.4
FIFO Overflow
If FIFO overflow occurs during Play mode (eg: as a result of motor rotational shock), the FIFO will be automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimise the effect of data loss.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
8. 8.1 FUNCTIONAL DESCRIPTION OF THE SERVO PART Diode Signal Processing
SAA7378GP
The photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. Four of these diodes (three for single focault systems) carry the central aperture (CA) signal while the other two diodes (satellite diodes) carry the radial tracking information. The CA signal is processed into an HF signal (for the decoder function) and LF signal (information for the focus servo loop) before it is supplied to the SAA7378. The analog signals from the central and satellite diodes are converted into a digital representation using analog to digital converters (ADCs). The ADCs are designed to convert unipolar currents into a digital code. The dynamic range of the input currents is adjustable within a given range which is dependent on the value of external resistor connected to IREFT. The maximum current for the central diodes and satellite diodes is given below: Iin(max, central) = (2.4 * 106 / RIREFT) A Iin(max, satellite) = (1.2 * 106 / RIREFT) A The VRH voltage is internally generated by control circuitry which takes care that the VRH voltage is adjusted depending upon the spread of internal capacitors, using the reference current generated by the external resistor on IREFT. In the application VRL is connected to VSSA1. The maximum input currents for a range of resistors is given below:
RIREFT () 220k 240k 270k 300k 330k 360k 390k 430k 470k 510k 560k 620k diode input current range D1,D2,D3,D4 R1,R2
(A)
(A)
10.909 10.000 8.889 8.000 7.273 6.667 6.154 5.581 5.106 4.706 4.286 3.871
5.455 5.000 4.444 4.000 3.636 3.333 3.077 2.791 2.553 2.353 2.143 1.935
This mode of VRH automatic adjustment can be selected by the preset latch command. Alternatively the dynamic range of the input currents can be made dependent on the ADC reference voltages; VRL and VRH, for this case the maximum current for the central diodes and satellite diodes is given below: Iin(max, central) = fsys * (VRH - VRL) * 1.0 * 10-6 A Iin(max, satellite) = fsys * (VRH - VRL) * 0.5 * 10-6 A where fsys = 4.2336MHz
VRH is generated internally, and there are 32 levels which can be selected under software control, via the preset latch command. With this command the VRH voltage can be set to 2.5V then modified, decremented one level or incremented, by resending the command the required number of times. In the application VRL is connected to VSSA1.
8.2
Signal Conditioning
The digital codes retrieved from the ADCs are applied to logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal: FEn = D1 - D2 D1 + D2 D3 - D4 D3 + D4
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
where the detector set up is assumed as shown in Figure 16.
SAA7378GP
Satellite diode R1
Satellite diode R1
Satellite diode R1
D1 D3 D2
D2 D1 D4 D3
D1 D2 D3 D4 Satellite diode R2 double Foucault
Satellite diode R2 single Foucault
Satellite diode R2 astigmatic focus
Figure 16
Detector Arrangement
In the case of single Foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows: FEn = 2 * D1 - D2 D1 + D2
The error signal, FEn, is further processed by a proportional integral and differential (PID) filter section. A focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the track-loss (TL) generation, the focus start up procedure and the drop out detection. The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows: REs = (R1 - R2) * re_gain + (R1 - R2) * re_offset
where the index 's' indicates the automatic scaling operation which is performed on the radial error signal. This scaling is necessary to avoid non-optimal dynamic range usage in the digital representation and reduces the radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start up of the disc. The four signals from the central aperture detectors together with the satellite detector signals generate a track position signal (TPI), which can be formulated as follows: TPI = sign [ (D1 + D2 + D3 + D4) - (R1 + R2) * sum_gain] Where the weighting factor sum_gain is generated internally, by the SAA7378, during initialisation.
8.3
Focus Servo System
The SAA7378 includes the following focus servo functions:
8.3.1
Focus Start-up
Five initially loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangle voltage can be influenced by 3 parameters; for height (ramp_height) and DC-offset (ramp_offset) of the triangle and its steepness (ramp_incr). For protection against false focus point detections two parameters are available, which are an absolute level on the CAsignal (CA_start) and a level on the FEn signal (FE_start). When this CA level is reached the FOK signal becomes true. If this FOK signal is true and the level on the FEn signal is reached, the focus PID is enabled to switch on when the next zero crossing is detected in the FEn signal.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
8.3.2 Focus Position Control Loop
SAA7378GP
The focus control loop contains a digital PID controller which has 5 parameters available to the user. These coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the PID and a digital low pass filter (foc_pole_noise, part of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop gain.
8.3.3
Drop-out Detection
This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false it is assumed, initially, to be caused by a black dot.
8.3.4
Focus Loss Detection and Fast Restart
Whenever FOK is false for longer than about 3ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300ms depending on the microprocessor programmed coefficients.
8.3.5
Focus Loop Gain Switching
The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be switched at the same time as the gain switching is performed.
8.4
Radial Servo System
The SAA7378 includes the following focus servo functions:
8.4.1
Level Initialisation
During start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI level generation. The initialisation procedure runs in a radial open loop situation and is 300ms. This start-up time period may coincide with the last part of the motor start up time period. Automatic gain adjustment: As a result of this initialisation the amplitude of the RE signal is adjusted within 10% around the nominal RE amplitude Offset adjustment: The additional offset in RE due to the limited accuracy of the start-up procedure is less than 50nm. TPI level generation: The accuracy of the initialisation procedure is such that the duty cycle range of TPI becomes 0.4 < dutycycle < 0.6 (def. dutycycle: TPI-'high' / TPI-period).
8.4.2
Sledge Control
The microprocessor can move the sledge in both directions via the steer sledge command.
8.4.3
Tracking Control
The actuator is controlled using a PID loop filter with user defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over 0.75 track. Upon request from the microprocessor S-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. Both modes of S-curve extension make use of a track-count mechanism. In this mode track counting results in an 'automatic return to zero track', to avoid major music rhythm disturbances in the audio output for improved shock resistance. The sledge is continuously controlled using the filtered value of the radial PID output. Alternatively the microprocessor can read the average voltage on the radial actuator, and provides the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control are user presettable.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
8.4.4 Access
ACCESS TYPE Actuator jump Sledge jump
1
SAA7378GP
The access procedure is divided into two different modes, depending upon the requested jump size.
JUMP SIZE 1 - brake_distance1 brake_distance1 - 32768 ACCESS SPEED decreasing velocity maximum power to sledge 1
: microprocessor presettable
The access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity setpoint calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. If the number of tracks to go is greater than brake_distance then the sledge jump mode should be activated else the actuator jump should be performed. The requested jump size together with the required sledge breaking distance at maximum access speed defines the value brake_distance. During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the radial PID output. All filter parameters (for actuator and sledge) are user programmable. In sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction, while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated).
8.5
Off Track Counting
The track position (TPI) signal is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 1/4 of the track-pitch. In combination with the radial polarity flag (RP) the relative spot position over the tracks can be determined. These signals are, however afflicted with some uncertainties caused by: * disc defects such as scratches and fingerprints. * the HF information on the disc, which is considered as noise by the detector signals. In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a track loss (TL) signal as well as an off-track counter value. These extra conditions influence the maximum speed and this implies that, internally, one of the three following counting states is selected: 1. 2. Protected state: used in normal play situations. A good protection against false detection caused by disc defects is important in this state. Slow counting state: used in low velocity track jump situations. In this state a fast response is important rather than the protection against disc defects (if the phase relationship between TL and RP of 1/2 radians is affected too much, the direction cannot be determined accurately anymore). Fast counting state: used in high velocity track jump situations. Highest obtainable velocity is the most important feature in this state.
3.
8.6
Defect Detection
A defect detection circuit is incorporated into the SAA7378. If a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. The defect detector can be switched off, applied only to focus control, or applied to both focus and radial controls under software control (part of foc_parm1). The defect detector (Figure 17) has programmable setpoints selectable by the parameter, defect_parm.
Sat1
+ -
+
Decimation filter
Fast filter
Slow filter
Defect generation
Programmable hold-off
Defect Out
Sat2
Figure 17
Defect Detector Block Diagram
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
8.7 Off Track Detection
SAA7378GP
During active radial tracking, off track detection has been realised by continuously monitoring the off track counter value. The off track flag becomes valid whenever the off track counter value is unequal to zero. Depending on the type of extended S-curve the off track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode.
8.8
Driver Interface
The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either 1.0584MHz (DSD mode) or 2.1168MHz; controlled via the xtra_preset parameter. An analog representation of the output signals can be achieved by connecting a first order low pass filter to the outputs. During reset (ie. RESET pin is held low) the RA, FO and SL pins are high impedance.
8.9
Laser Interface
The LDON pin (open drain output) is used to switch the laser off and on; when the laser is on the output is high impedance. The action of the LDON pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active.
8.10
Radial Shock Detector
The shock detector (block diagram shown in Figure 18) can be switched on during normal track following; and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level). Every time the radial tracking error (RE) exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4.
RE
High pass filter (0 or 20Hz)
Low pass filter (750 or 1850Hz)
Amplitude detection
Shock out
Figure 18
Block Diagram of Shock Detector
The shock detection level is adjustable in 16 steps from 0 to 100% of the traverse radial amplitude which is sent to an amplitude detection unit via an adjustable bandpass filter (controlled by sledge_parm1); lower corner frequency can be set at either 0 or 20Hz, and upper corner frequency at 750 or 1850Hz. The shock detector is switched off automatically during jump mode.
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
9. MICROPROCESSOR INTERFACE
SAA7378GP
Communication on the microprocessor interface is via a 4-wire bus: the protocol being compatible with SAA7345 (CD6) and TDA1301 (DSIC2): SCL - serial bit clock. SDA - serial data. RAB - R/W control and data strobe (active high) for writing to registers 0 - F, reading status bit selected via register 2 and reading Q channel subcode. SILD - R/W control and data strobe (active low) for servo commands.
9.1
Writing Data to Registers 0 - E
The sixteen 4-bit programmable configuration registers, 0 to E (Table 1), can be written to via the microprocessor interface using the protocol shown in Figure 19.
RAB (P) SCL (P) SDA (P) SDA (SAA7378) A3 A2 A1 A0 D3 D2 D1 D0
Hi-impedance
Figure 19
Microprocessor Write Protocol for Registers 0 to E
Note that: - SILD must be held high. - A(3:0) identifies the register number, D(3:0) is the data. - the data is latched into the register on the low-high transition of RAB.
9.1.1
Writing Repeated Data to Registers 0 - E
The same data can be repeated several times (eg: for a fade function) by applying extra RAB pulses as shown in Figure 20. Note that SCL must stay high between RAB pulses.
RAB (P) SCL (P) SDA (P) SDA (decoder) A3 A2 A1 A0 D3 D2 D1 D0
Hi-impedance
Figure 20
Microprocessor Write Protocol for Registers 0 to E - Repeat Mode
9.2
Reading Decoder Status Information on SDA
There are several internal status signals, selected via register 2, which can be made available on the SDA line. These are: Low if new subcode word is ready in Q-channel register. - SUBQREADY-I - MOTSTART1 High if motor is turning at 75% or more of nominal speed. - MOTSTART2 High if motor is turning at 50% or more of nominal speed. - MOTSTOP High if motor is turning at 12% or less of nominal speed. Can be set to indicate 6% or less (instead of 12% or less) via register E. - PLL Lock High if Sync coincidence signals are found. - V1 Follows input on V1 pin.
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Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
- V2 Follows input on V2 pin. - MOTOR-OV High if the motor servo output stage saturates. - FIFO-OV High if FIFO overflows. - SHOCK MOTSTART2 + PLL Lock + MOTOR-OV + FIFO-OV + OTD (high if shock detected) - LA-SHOCK Latched SHOCK signal The status read protocol is shown in Figure 21.
RAB (P) SCL (P) SDA (P) SDA (SAA7378) Hi-impedance STATUS
Figure 21
Microprocessor Read Protocol for Decoder Status on SDA
Note that: - SILD must be held high.
9.3
Reading Q-Channel Subcode
To read Q-channel subcode direct in 4-wire bus mode, the SUBQREADY-I signal should be selected as status signal. The subcode read protocol is shown in Figure 22.
RAB (P) SCL (P) SDA (SAA7378) CRC Q1 OK STATUS Q2 Q3 Qn-2 Qn-1 Qn
Figure 22
Microprocessor Protocol for Reading Q-Channel Subcode
Note that: - SILD must be held high. - after subcode read starts, the microprocessor may take as long as it wants to terminate the read operation. - when enough subcode has been read (1 - 96 bits), terminate reading by pulling RAB low.
9.3.1
Behaviour of the SUBQREADY-I Signal
When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as shown in Figure 23:
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
RAB (P) SCL (P) SDA (SAA7378) High impedance CRC OK
10.8ms 2.3 ms 15.4ms
CRC OK
Read start allowed
Figure 23
SUBQREADY-I Status Timing when no Subcode is Read
When the CRC is good and subcode is being read, the timing in Figure 24 applies:
t2 t1 RAB (P) SCL (P) SDA (SAA7378) Q1 Q2 Q3 Qn t3
Figure 24
SUBQREADY-I Status Timing when Subcode is Read
If t1 (SUBQREADY-I status low to end of subcode read) is below 2.6ms, then t2 = 13.1ms [ie: the microprocessor can read all subcode frames if it completes the read operation within 2.6ms after the subcode is ready]. If this criterion is not met, it is only possible to guarantee that t3 will be below 26.2ms (approximately). If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by 13.1ms for each defective subcode frame.
9.4
Write Servo Commands
A write data command is used to transfer data (a number of bytes) from the microprocessor, using the protocol shown in Figure 25. The first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. Note that: - RAB must be held low. - The command or data is interpreted by the SAA7378 after the high-low transition of SILD. - There must be a minimum time of 65s between SILD pulses.
9.4.1
Writing Repeated Data In Servo Commands
The same data byte can be can be repeated by applying extra SILD pulses as shown in Figure 26. SCL must stay high
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
between the SILD pulses.
SAA7378GP
SILD (P) SCL (P) SDA (P) SDA (SAA7378) D7 D6 D5 D4 D3 D2 D1 Command or Data byte Hi-impedance Microprocessor write (one byte : command or data) D0
SILD (P) SDA (P)
Command Data1 Data2 Data3
Microprocessor write (full command)
Figure 25
Microprocessor Protocol for Write Servo Commands
SILD (P) SDA (P)
Command Data1
Microprocessor write (full command)
Figure 26
Microprocessor Protocol for Repeated Data in Write Servo Commands
9.5
Read Servo Commands
A read data command is used to transfer data (status information) to the microprocessor, using the protocol shown in Figure 27. The first byte written determines the type of command. After this byte a variable number of bytes can be read. Note that: - RAB must be held low. - After the end of a read command there must be a delay of 65s before a write command is started. - There must be a minimum time of 65s between SILD pulses.
SILD (P) SCL (P) SDA (SAA7378) D7 D6 D5 D4 D3 Data byte D2 D1 D0
Microprocessor read (one data byte) SILD (P) SDA (SAA7378) SDA (P)
Command Data1 Data2 Data3
Microprocessor read (full command)
Figure 27
Microprocessor Protocol for Read Servo Commands
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
9.6
Table 1
SAA7378GP
Summary of Functions Controlled by Registers 0 to E
Registers 0 to E
ADDRESS 0000 DATA 0000 0010 0001 0100 0101 1 (Motor mode) 0001 x000 x001 x010 x011 x100 x101 x111 x110 1xxx 0xxx 2 (Status control) 0010 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 3 (DAC output) 0011 1100 1111 0000 0011 0100 0111 FUNCTION Mute Attenuate Full Scale Step Down Step Up Motor off mode Motor stop mode 1 Motor stop mode 2 Motor start mode 1 Motor start mode 2 Motor jump mode Motor play mode Motor jump mode 1 anti-windup active anti-windup off status = SUBQREADY-I status = MOTSTART1 status = MOTSTART2 status = MOTSTOP status = PLL Lock status = V1 status = V2 status = MOTOR-OV Status = FIFO overflow Status = Shock Detect Status = Latched Shock Detect Status = Latched Shock Detect Reset I2S - 18 bit - 4fs mode I2S - 18 bit - 2fs mode EIAJ - 16 bit - 4fs EAIJ - 16 bit - 2fs EIAJ - 18 bit - 4fs EIAJ - 18 bit - 2fs Reset Reset Reset Reset INITIAL Reset
The INITIAL column shows the power-on reset state
REGISTER 0 (Fade and Attenuation)
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
Table 1 Registers 0 to E
ADDRESS 0100 DATA x000 x001 x010 x011 x100 x101 x110 x111 0xxx 1xxx 5 (Motor bandwidth) 0101 xx00 xx01 xx10 xx11 00xx 01xx 10xx 6 (Motor output configuration) 0110 xx00 xx01 xx10 xx11 00xx 01xx 10xx 11xx 7 (DAC output) 0111 x000 x100 0xxx 1xxx 8 (PLL loop filter bandwidth) 1000 0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110 FUNCTION Motor gain G = 3.2 Motor gain G = 4.0 Motor gain G = 6.4 Motor gain G = 8.0 Motor gain G = 12.8 Motor gain G = 16.0 Motor gain G = 25.6 Motor gain G = 32.0 Disable comparator clock divider
SAA7378GP
REGISTER 4 (Motor gain)
INITIAL Reset
Reset Reset
Enable comparator clock divider; only if SELLPLL set high Motor f4 = 0.5Hz Motor f4 = 0.7Hz Motor f4 = 1.4Hz Motor f4 = 2.8Hz Motor f3 = 0.85Hz Motor f3 = 1.71Hz Motor f3 = 3.42Hz Motor power max. 37% Motor power max. 50% Motor power max. 75% Motor power max. 100% MOTO1, MOTO2 pins tri-state Motor PWM mode Motor PDM mode Motor CDV mode DAC data normal value DAC data inverted value L channel first at DAC (WCLK normal) R channel first at DAC (WCLK inverted) Loop BW Hz 1640 3279 6560 1640 3279 6560 1640 3279 6560 1640 3279 6560 Int. BW Hz 525 263 131 1050 525 263 2101 1050 525 4200 2101 1050 Low-pass BW Hz 8400 16800 33600 8400 16800 33600 8400 16800 33600 8400 16800 33600 Reset Reset Reset Reset Reset Reset
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Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
Table 1 Registers 0 to E
ADDRESS 1001 DATA 0011 0001 0010 0100 0101 A (EBU output) 1010 x010 x011 x110 x111 0xxx 1xxx B 1011 00xx 01xx xx00 xx10 xx11 C (Versatile pins interface) 1100 xxx1 xxx0 xx0x 001x 011x D (Versatile pins interface) 1101 0000 xx10 xx11 01xx 10xx 11xx E 1110 0100 0101 FUNCTION PLL loop filter equalisation PLL 30ns over-equalisation PLL 15ns over-equalisation PLL 15ns under-equalisation PLL 30ns under-equalisation Level II clock accuracy (<1000ppm) Level I clock accuracy (<50ppm) Level III clock accuracy (>1000ppm) EBU off - output low Flags in EBU off Flags in EBU on 33.8688MHz crystal present, or 8.4672MHz crystal with SELPLL set high 16.9344MHz crystal present Standby 1 : 'CD-STOP' mode Standby 2 : 'CD-PAUSE' mode Operating mode External offtrack signal input at V1
SAA7378GP
REGISTER 9 (PLL equalisation)
INITIAL Reset
Reset
Reset Reset
Reset
Internal offtrack signal used (V1 may be read via status) Kill-L at KILL output, Kill-R at V3 output V3 = 0; single Kill output V3 = 1; single Kill output 4-line motor (using V4, V5) V4 = 0 V4 = 1 De-emphasis signal at V5, no internal de-emphasis filter V5 = 0 V5 = 1 Motor brakes to 12% Motor brakes to 6%
Reset Reset
Reset
Reset Reset
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Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
9.7 Summary of Servo Commands
SAA7378GP
A list of the servo commands are given below; note that these are not fully backwards compatible with DSIC2: Table 2 CD7 Servo Commands.
code Write_focus_coefs1 Write_focus_coefs2 Write_focus_command Focus_gain_up Focus_gain_down Write_radial coefs Preset_Latch Radial_off Radial_init Short_jump Long_jump Steer_sledge Preset_init Write_parameter READ COMMANDS code Read_status Read_aux_status 70h F0h bytes up to 5 up to 3 parameters 17h 27h 33h 42h 62h 57h 81h C1h C1h C3h C5h B1h 93h A2h bytes 7 7 3 2 2 7 1 1 1 3 5 1 3 2 parameters "1Ch" "3Ch"
WRITE COMMANDS
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Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
9.7.1 Summary of Servo Command Parameters
parameter RAM addr. 14h 15h 12h 16h 18h 19h 28h 29h 1Ch 1Eh 2Ah 27h 1Fh 32h 48h 49h 21h 58h 36h 17h affects focus PID focus PID focus PID focus PID focus PID focus PID focus ramp focus ramp focus ramp focus ramp radial PID radial PID radial PID radial PID radial PID radial jump radial jump radial jump radial jump radial jump radial jump radial jump sledge sledge sledge sledge 7Fh 00h 70h 70h POR value determines end of focus lead defect detector enabling focus low pass focus error normalising focus lead length minimum light level focus integrator crossover freq focus PID loop gain sensitivity of drop-out detector assymetry of focus ramp p-p value of ramp voltage slope of ramp voltage minimum value of focus error end of radial lead radial low-pass length of radial lead radial integrator crossover freq radial loop gain filter during jump PI controller crossover freqs jump pre-defined profile maximum speed in fastrad mode sledge bandwidth during jump
SAA7378GP
A list of the servo command parameters are given below:
foc_parm_1 foc_parm_2 foc_parm_3 foc_int foc_gain CA_drop ramp_offset ramp_height ramp_incr FE_start rad_parm_play rad_pole_noise rad_length_lead rad_int rad_gain rad_parm_jump vel_parm1 vel_parm2 speed_threshold hold_mult brake_dist_max sledge_long_brake sledge_Umax sledge_level sledge_parm_1 sledge_parm_2
max sledge distance allowed in fast actuator steered mode brake distance of sledge voltage on sledge during long jump voltage on sledge when steered sledge integrator crossover freq sledge low pass freqs sledge gain sledge operation mode defect detector setting shock detector operation VRH level setting 38h laser on/off RA, FO, SL PDM modulating freq. initialisation initialisation initialisation initialisation
defect_parm shock_level chip_init xtra_preset config_parm1 config_parm2 config_parm3 config_parm4
4Ah 42h 53h 59h 68h
defect detector shock detector setup setup setup setup setup setup
May 1995
34
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
10. 10.1
SYMBOL Supply VDD IDD supply voltage supply current Comparator Inputs, HFIN, HFREF: fcomp Vth Vtpt VIREF clock frequency switching thresholds HFIN input level Reference Generator, IREF: reference voltage at IREF pin VDD/2 see Note 1 8 1.2 1.0 VDD = 5 V 3.4 5.0 49
SAA7378GP
OPERATING CHARACTERISTICS General Characteristics
PARAMETER CONDITIONS MIN TYP 5.5 MAX UNIT V mA
VDD = 3.4 to 5.5 V; VSS = 0; Tamb = 5 to 70 C; unless otherwise stated.
Decoder Analogue Front-End (VDD = 5.0 V; VSS = 0; Tamb = 25 C) 70 VDD - 0.8 MHz V V V
Servo Analogue Part (VDD = 5.0 V; VSS = 0; Tamb = 25 C) Pins D1, D2, D3, D4, R1, R2, VRH, VRL, IREFT: IIREFT RIREFT VIREFT ID IR VRL VRH input current for IREFT external resistor on IREFT voltage on current input IREFT maximum input current for central diode input signal maximum input current for satellite diode input signal LOW level reference voltage HIGH level reference voltage see Note 3 output state 0 output state v output state 31 (THD+N)/S total harmonic distortion plus noise S/N PSRR Gtol G a signal to noise ratio power supply rejection at VDDA2 gain tolerance variation of gain between channels channel separation see Note 4 see Note 6 at 0 dB; see Note 5 -30% -12 0.5 .5*10 2.5 -50 55 45 0 60
v/44.4
1.935 220 see Note 2 see Note 2 3.871 1.935 0
1.2 0
5.45 620 10.9 5.45 0 +30% -45 +12 2 -
A k V A A V V V V dB dB dB % % d
May 1995
35
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
SYMBOL Digital Inputs
PARAMETER Input: RESET, V1, V2, SELPLL
CONDITIONS
MIN
TYP
MAX
UNIT
CMOS input with pullup and hysteresis 0.2 x VDD VIN = 0 RESET only CMOS input -0.3 0.7 x VDD VIN = 0 - VDD -10 0.3 x VDD VDD + 0.3 +10 10 V V 1 0.33 x VDD 50 0.8 x VDD 10 V V V k pF
VTHR VTHF Vhys RPU CIN tRW VIL VIH IIN CIN
switching threshold rising switching threshold falling hysteresis voltage input pull-up resistance input capacitance reset pulse width (active low) Input: SCL, RAB, SILD input voltage LOW input voltage HIGH input leakage current input capacitance Outputs: CL4
s
A
pF
Digital Output VOL VOH CL tR tF VOL VOH CL tR tF VOL VOH CL tR tF output voltage LOW output voltage HIGH load capacitance output rise time (CL = 20 pF) output fall time (CL = 20 pF) Outputs: CL16 output voltage LOW output voltage HIGH load capacitance output rise time (CL = 20 pF) output fall time (CL = 20 pF) Outputs: V4, V5 output voltage LOW (VDD = 4.5 to 5.5 V) IOL = + 10 mA output voltage LOW (VDD = 3.4 to 5.5 V) IOL = + 5 mA output voltage HIGH (VDD = 4.5 to 5.5 V) IOH = -10 mA output voltage HIGH (VDD = 3.4 to 5.5 V) IOH = -5 mA load capacitance output rise time (CL = 20 pF) output fall time (CL = 20 pF) 0.8 - (VDD - 0.8) (VDD - 0.8) -0.8 0 0 VDD - 1 VDD - 1 1.0 1.0 VDD VDD 50 10 10 V V V V pF ns ns 0.8 - (VDD - 0.8) (VDD - 0.8) - 0.8 IOL = +1 mA IOH = -1 mA 0 VDD - 0.4 0.4 VDD 50 15 15 V V pF ns ns 0.8 to (VDD - 0.8) (VDD - 0.8) to 0.8 IOL = + 1 mA IOH = - 1 mA 0 VDD - 0.4 0.4 VDD 25 20 20 V V pF ns ns
May 1995
36
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
SYMBOL Open Drain Outputs
PARAMETER Outputs: CFLG, STATUS, KILL, V3, LDON
CONDITIONS
MIN
TYP
MAX
UNIT
Open drain output with protection diode to VDD IOL = +1 mA 0 (VDD - 0.8) - 0.8 0.4 2 25 30 V mA pF ns
VOL IOL CL tF
output voltage LOW output current load capacitance output fall time (CL = 20 pF) Outputs: SCLK, WCLK, DATA, CL11
Tri-State Outputs VOL VOH CL tR tF IIN tHIGH VOL VOH CL tR tF IIN VOL VOH CL tR tF IIN output voltage LOW output voltage HIGH load capacitance output rise time (CL = 20 pF) output fall time (CL = 20 pF) tri-state leakage current Output: CL11 output high time (relative to clock period) VO = 1.5 V Outputs: RA, FO, SL output voltage LOW output voltage HIGH load capacitance output rise time (CL = 20 pF) output fall time (CL = 20 pF) tri-state leakage current Outputs: MOTO1, MOTO2, DOBM output voltage LOW (VDD = 4.5 to 5.5 V) IOL = +10 mA output voltage LOW (VDD = 3.4 to 5.5 V) IOL = +5 mA output voltage HIGH (VDD = 4.5 to 5.5 V) IOH = -10 mA output voltage HIGH (VDD = 3.4 to 5.5 V) IOH = -5 mA load capacitance output rise time (CL = 20 pF) output fall time (CL = 20 pF) tri-state leakage current 0.8 - (VDD - 0.8) (VDD - 0.8) -0.8 VIN = 0 - VDD 0 0 VDD - 1 VDD - 1 - 10 1.0 1.0 VDD VDD 50 10 10 +10 V V V V pF ns ns 0.8 - (VDD - 0.8) (VDD - 0.8) - 0.8 VIN = 0 - VDD IOL = +1 mA IOH = -1 mA 0 VDD - 0.4 -10 0.4 VDD 25 20 20 +10 V V pF ns ns 45 50 55 % 0.8 - (VDD - 0.8) (VDD - 0.8) - 0.8 VIN = 0 - VDD IOL = +1 mA IOH = -1 mA 0 VDD - 0.4 -10 0.4 VDD 50 15 15 +10 V V pF ns ns
A
A
A
May 1995
37
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
SYMBOL Digital Input/Output
PARAMETER Input/Output: SDA
CONDITIONS
MIN
TYP
MAX
UNIT
CMOS input/open drain output (with protection diode to VDD) -0.3 0.7 x VDD VIN = 0 - VDD IOL = +2 mA -10 0 (VDD - 0.8) - 0.8 0.3 x VDD VDD + 0.3 +10 10 0.4 4 50 15 V V
VIL VIH IIN CIN VOL IOL CL tF
input voltage LOW input voltage HIGH tri-state leakage current input capacitance output voltage LOW output current load capacitance output fall time (CL = 20 pF) Input: CRIN (external clock)
A
pF V mA pF ns
Crystal Oscillator VIL VIH IIN CIN fc gm AV CF COUT Notes: 1) 2) input voltage LOW input voltage HIGH input leakage current input capacitance Output: CROUT crystal frequency mutual conductance at 100kHz small signal voltage gain feedback capacitance output capacitance AV = gm * RO see Figure 3 see Note 7 8 8.4672 10 18 35 5 10 MHz mA/V -0.3 0.7 x VDD -10 0.3 x VDD VDD + 0.3 +10 10 V V
A
pF
V/V
pF pF
Highest clock frequency at which data slicer produces 1010 output in analogue self-test mode. VRL = 0V, fsys=4.2336MHz. The maximum input current depends on the value of the external resistor connected to IREFT. For D1 to D4: For R1 and R2: Imax = 2.4 / RIREFT 2.4 / 220k = 10.9A. Imax = 1.2 / RIREFT 1.2 / 220k = 5.45A.
3) 4) 5) 6)
Internal reference source with 32 different output voltages. Selection is achieved during a calibration period or via the serial interface. The values given are for an unloaded VRH. fripple = 1 kHz, Vripple = 0.5 Vp-p. VRH = 2.5 V and VRL = 0 V, measuring bandwidth: 200 Hz - 20 kHz, fin(ADC) = 1 kHz. Gain of the ADC is defined as : G(ADC) = fsys/Imax (counts/A) Thus digital output = II x G(ADC) where: Digital output = the number of pulses at the digital output in counts/s and II = the DC input current in A. The maximum input current depends on the system frequency (fsys=4.2336MHz) and on VRH - VRL. The gain tolerance is the deviation from the calculated gain regarding Note 2.
7)
It is recommended that the series resistance of the crystal or ceramic resonator is 60.
May 1995
38
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
10.2
SYMBOL
2
SAA7378GP
Operating Characteristics (I2S Timing)
PARAMETER Clock output: SCLK (CL = 20pF) CONDITIONS MIN TYP MAX UNIT
VDD = 3.4 to 5.5 V; VSS = 0; Tamb = 5 to 70 C; unless otherwise stated.
I S Timing; see Figure 28 tPO tHC tLC output clock period sample rate = fs sample rate = 2 fs sample rate = 4 fs sample rate = fs 166 sample rate = 2 fs 83 sample rate = 4 fs 42 sample rate = fs 166 sample rate = 2 fs 83 sample rate = 4 fs 42 sample rate = fs 95 sample rate = 2 fs 48 sample rate = 4 fs 24 sample rate = fs 95 sample rate = 2 fs 48 sample rate = 4 fs 24 472.4 236.2 118.1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
clock HIGH time
clock LOW time
Outputs: WCLK, DATA, EF (CL = 20pF) tST tHT setup time
hold time
clock period tPO tLC tHC VDD-0.8 V
SCLK
0.8 V
tHT
tST
WCLK DATA EF
VDD-0.8 V
0.8 V
Figure 28
I2S Timing
May 1995
39
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
10.3 Operating Characteristics (P Interface Timing)
SYMBOL PARAMETER CONDITIONS MIN TYP
SAA7378GP
VDD = 3.4 to 5.5 V; VSS = 0; Tamb = 5 to 70 C; unless otherwise stated. MAX UNIT
P interface timing (writing to registers 0 to F; reading Q-channel subcode and decoder status) see Figure 29 and Figure 30.
Inputs SCL and RAB tL tH tR tF tDRD tDD tDRZ tSD tHD tSCR tDWZ input LOW time input HIGH time rise time fall time Read mode (CL = 20pF) delay time RAB to SDA valid propagation delay SCL to SDA delay time RAB to SDA hi-impedance Write mode (CL = 20pF) setup time SDA to SCL hold time SCL to SDA setup time SCL to RAB delay time SDA hi-impedance to RAB Inputs SCL and SILD tL tH tR tF tDLD tDD tDLZ tSD tHD tSCL tHCL tPLP tDWZ Notes: 1) Input LOW time Input HIGH time rise time fall time Read mode (CL = 20pF) delay time SILD to SDA valid propogation delay SCL to SDA delay time SILD to SDA hi-impedance Write mode (CL = 20pF) set up time SDA to SCL hold time SCL to SDA aet up time SCL to SILD hold time SILD to SCL delay between two SILD pulses delay time SDA hi-impedance to SILD 0 950 480 120 65 0 ns ns ns ns s ns 25 950 50 ns ns ns 710 710 240 240 ns ns ns ns note 1 -700 260 0 980 ns ns ns ns 700 50 980 50 ns ns ns 500 500 480 480 ns ns ns ns
P interface timing (servo commands) see Figure 31 and Figure 32.
Negative set-up time means that the data may change after clock transition.
May 1995
40
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
RAB
VDD - 0.8 V 0.8 V tR tR VDD - 0.8 V 0.8 V tDRD tDD tDRZ tF tF
SCL
SDA (SAA7378)
VDD - 0.8 V 0.8 V
Figure 29
Microprocessor Timing (Q-channel subcode and decoder status information) - Read Mode
RAB
tH
VDD - 0.8 V 0.8 V tSCR tL tH
SCL
VDD - 0.8 V 0.8 V tSD tHD tL tDWZ
SDA(P)
VDD - 0.8 V 0.8 V
Figure 30
Microprocessor Timing (Registers 0 to E) - Write Mode
SILD
0.8 V
VDD - 0.8 V
SCL
tDD tDLD tDLZ
SDA (SAA7378)
VDD - 0.8 V 0.8 V
Figure 31
Microprocessor Timing (servo commands) - Read Mode
May 1995
41
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
SAA7378GP
SILD
tH
VDD - 0.8 V 0.8 V tSCL tL tPLP VDD - 0.8 V 0.8 V tSD VDD - 0.8 V 0.8 V tHD tL tDWZ tHCL
SCL
SDA(P)
Figure 32
Microprocessor Timing (servo commands) - Write Mode
May 1995
42
11.
64
63
62
60
58
57
56
55
54
52
51
50
V2
SCL
VSS4
SILD 53 RAB
SDA
CL4
+V
LDON
VDD 1 100nF 2 100nF 3 220pF 4 47
V1 61 CFLG
TEST10 VDD3C 59
RESET
(3)
VDDA
2.2
TEST9
TDA1300
VSSA1 VDDA1 D1 D2 D3
43
49
VDD1P
IREF
VDDA2
TEST1
CRIN CROUT
TEST2
CL16
CL11 RA
FO
SL TEST3
47pF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
22nF (1) (2)
Digital Servo Processor and Compact Disc Decoder (CD7)
to power amplifiers VDD
2.2 100nF
to DOBM transformer
(1) Diagram is for a 5V application. For 3.4V applications an additional resistor of 150k should be added between IREF (pin 18) and ground. (2) For crystal oscillator circuit see Figure 3. (3) The connections to TDA1300 are shown for single foucault mechanisms.
Preliminary specification: Version 1.0
SAA7378GP
Figure 33
Typical SAA7378 application diagram
DOBM
May 1995
+V +V +V
micro-controller interface
VDD 4.7k 4.7k
2.2
Philips Semiconductors
+
33F
100nF 100nF
VSS3 SCLK VDD2P 46 WCLK DATA TEST8 KILL 42 V3
44 45 48 2.2
LDON 7 to DAC
33F
+
D2 6
220pF 5 6 220pF 220pF 220pF 8
3
APPLICATION INFORMATION
D3 D4 1 VRL 7 D4 R1
220pF 9
100k
D1 4 V4 V5
39 40 41
100k
D5 5
D6 2 R2 IREFT VRH VSSA2 SELPLL
35 10 270k 12 11
SAA7378
VSS2 38 TEST7 TEST6 TEST5 TEST4 34 MOTO2 MOTO1 VSS1
33 36 37
motor interface
43
13 14 15 VDDA 100nF 16
RFE 9
100nF
22k
ISLICE HFIN VSSA3 HFREF
2.2nF
2.2k
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
12. PACKAGE OUTLINE
SAA7378GP
May 1995
44
Figure 34
64-lead quad flat-pack; plastic (SOT393-1)
Philips Semiconductors
Preliminary specification: Version 1.0
Digital Servo Processor and Compact Disc Decoder (CD7)
13. 13.1 13.1.1 SOLDERING Plastic quad flat-packs BY WAVE
SAA7378GP
During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is reccommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications.
13.1.2
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Prehaeting is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C.
13.1.3
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
14.
DEFINITIONS
Data sheet status Objective specification Preliminary specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later This data sheet contains final product specifications.
15.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
May 1995
45

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